: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1463757	245	0	0
SrcPulseCheck_M	114159268	245	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1463757	245
T135	910	2
T136	6165	13
T137	2846	8
T333	5990	9
T335	748	1
T336	971	2
T337	3038	5
T361	2570	2
T362	2925	8
T368	686	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	114159268	245
T135	79624	2
T136	674545	13
T137	304982	8
T333	675595	9
T335	52264	1
T336	77522	2
T337	318375	5
T361	277631	2
T362	321849	8
T368	40076	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	114159268	245	0	0
SrcPulseCheck_M	1463757	245	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	114159268	245
T135	79624	2
T136	674545	13
T137	304982	8
T333	675595	9
T335	52264	1
T336	77522	2
T337	318375	5
T361	277631	2
T362	321849	8
T368	40076	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1463757	245
T135	910	2
T136	6165	13
T137	2846	8
T333	5990	9
T335	748	1
T336	971	2
T337	3038	5
T361	2570	2
T362	2925	8
T368	686	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1463757	254	0	0
SrcPulseCheck_M	114159268	254	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1463757	254
T135	910	2
T136	6165	15
T137	2846	4
T333	5990	18
T334	3208	8
T335	748	1
T336	971	2
T361	2570	2
T362	2925	6
T368	686	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	114159268	254
T135	79624	2
T136	674545	15
T137	304982	4
T333	675595	18
T334	357139	8
T335	52264	1
T336	77522	2
T361	277631	2
T362	321849	6
T368	40076	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	114159268	254	0	0
SrcPulseCheck_M	1463757	254	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	114159268	254
T135	79624	2
T136	674545	15
T137	304982	4
T333	675595	18
T334	357139	8
T335	52264	1
T336	77522	2
T361	277631	2
T362	321849	6
T368	40076	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1463757	254
T135	910	2
T136	6165	15
T137	2846	4
T333	5990	18
T334	3208	8
T335	748	1
T336	971	2
T361	2570	2
T362	2925	6
T368	686	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1463757	247	0	0
SrcPulseCheck_M	114159268	247	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1463757	247
T135	910	2
T136	6165	12
T137	2846	4
T333	5990	8
T335	748	1
T336	971	2
T337	3038	8
T361	2570	5
T362	2925	5
T368	686	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	114159268	247
T135	79624	2
T136	674545	12
T137	304982	4
T333	675595	8
T335	52264	1
T336	77522	2
T337	318375	8
T361	277631	5
T362	321849	5
T368	40076	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	114159268	247	0	0
SrcPulseCheck_M	1463757	247	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	114159268	247
T135	79624	2
T136	674545	12
T137	304982	4
T333	675595	8
T335	52264	1
T336	77522	2
T337	318375	8
T361	277631	5
T362	321849	5
T368	40076	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1463757	247
T135	910	2
T136	6165	12
T137	2846	4
T333	5990	8
T335	748	1
T336	971	2
T337	3038	8
T361	2570	5
T362	2925	5
T368	686	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1463757	236	0	0
SrcPulseCheck_M	114159268	236	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1463757	236
T135	910	2
T136	6165	4
T137	2846	3
T333	5990	13
T335	748	1
T336	971	2
T337	3038	3
T361	2570	6
T362	2925	6
T368	686	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	114159268	236
T135	79624	2
T136	674545	4
T137	304982	3
T333	675595	13
T335	52264	1
T336	77522	2
T337	318375	3
T361	277631	6
T362	321849	6
T368	40076	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	114159268	236	0	0
SrcPulseCheck_M	1463757	236	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	114159268	236
T135	79624	2
T136	674545	4
T137	304982	3
T333	675595	13
T335	52264	1
T336	77522	2
T337	318375	3
T361	277631	6
T362	321849	6
T368	40076	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1463757	236
T135	910	2
T136	6165	4
T137	2846	3
T333	5990	13
T335	748	1
T336	971	2
T337	3038	3
T361	2570	6
T362	2925	6
T368	686	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1463757	262	0	0
SrcPulseCheck_M	114159268	262	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1463757	262
T135	910	2
T136	6165	15
T137	2846	8
T333	5990	16
T335	748	1
T336	971	2
T337	3038	1
T361	2570	6
T362	2925	2
T368	686	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	114159268	262
T135	79624	2
T136	674545	15
T137	304982	8
T333	675595	16
T335	52264	1
T336	77522	2
T337	318375	1
T361	277631	6
T362	321849	2
T368	40076	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T335,T136
1	1	Covered	T135,T136,T137

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T335,T136
1	0	Covered	T135,T136,T137
1	1	Covered	T135,T335,T136

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	114159268	262	0	0
SrcPulseCheck_M	1463757	262	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	114159268	262
T135	79624	2
T136	674545	15
T137	304982	8
T333	675595	16
T335	52264	1
T336	77522	2
T337	318375	1
T361	277631	6
T362	321849	2
T368	40076	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1463757	262
T135	910	2
T136	6165	15
T137	2846	8
T333	5990	16
T335	748	1
T336	971	2
T337	3038	1
T361	2570	6
T362	2925	2
T368	686	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE 34 EXPRESSION (src_level ^ src_pulse_i) ----1---- -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T12,T14,T15
1	1	Covered	T14,T15,T24

 LINE 97 EXPRESSION (dst_level_q ^ dst_level) -----1----- ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T14,T15
1	0	Covered	T14,T15,T24
1	1	Covered	T14,T15,T24

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00


LineNo.Expression-1-:31if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3


LineNo.Expression-1-:89if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1463757	269	0	0
SrcPulseCheck_M	114159268	272	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1463757	269
T14	564	1
T15	0	4
T16	0	2
T18	0	2
T24	0	1
T48	0	4
T51	0	4
T57	8463	0
T60	1864	0
T98	0	2
T99	0	2
T109	1453	0
T112	472	0
T124	936	0
T210	844	0
T275	768	0
T315	961	0
T369	0	2
T370	562	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	114159268	272
T4	131450	0
T12	27569	1
T14	0	2
T15	0	4
T16	0	2
T18	0	2
T24	0	2
T48	0	4
T51	0	4
T56	40585	0
T58	60622	0
T59	57485	0
T84	54724	0
T85	35780	0
T98	0	2
T99	0	2
T100	57234	0
T101	41160	0
T102	22000	0

: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req (2024)

References